1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming MIS (Metal-Insulator-Semiconductor) contact structures for semiconductor devices and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
Irrespective of whether a planar or non-planar device is considered, electrical connections must be formed to the device so that it may operate as intended. That is, electrical connection must be made to the source region, the drain region and the gate electrode of the device. Typically, the conductive structures that actually make contact with the device itself, i.e., the source region, the drain region and the gate electrode, are referred to as “contacts” within the industry. Such conductive contacts are formed in one or more layers of insulating material. The entire arrangement of the conductive contacts and the associated layer(s) of insulating material is sometimes referred to as the “contact level” of the overall electrical “wiring arrangement” that is formed to provide electrical connection to the integrated circuit device.
The ongoing decrease in device dimensions also mandated an associated decrease in physical size of the contact openings (and contacts) that are formed to establish electrical connections to, for example, the source/drain regions. That is, there is very little room in the contact openings for all of the layers of material that are needed when forming conductive contact structures. Device designers have explored using different contact methods and structures to improve the operational characteristics of the devices and/or to simplify processing techniques. For example, U.S. Pat. No. 8,110,887 is an example of an MIS (Metal-Insulator-Semiconductor) contact structure for silicon-based transistor devices. However, what is needed for modern, high packing density applications, is an MIS contact structure that is more efficient and effective in terms of its use of space and the formation of a lower resistance structure.
The present disclosure is directed to various methods of forming MIS contact structures for semiconductor devices and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.